(a) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, such as a flash EEPROM., and more particularly, to a nonvolatile semiconductor memory device having a program area in each memory cell.
(b) Description of the Related Art
A flash EEPROM is known in the art having a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix and each having a double layer gate structure. Referring to FIG. 1 showing a schematic sectional view of a memory cell in a conventional EEPROM, the memory cell includes a floating gate FG formed on a semiconductor substrate having source and drain regions "S" and "D", with an intervention of a gate oxide film not shown, and a control electrode CG formed on the floating electrode FG with an intervention of another oxide film not shown.
In programming of the memory cell in FIG. 1, for example, electrons are withdrawn from the floating gate FG by applying a programming voltage between the control gate CG and the drain, whereas in erasing of the memory cell, electron is injected into the floating gate FG by applying an erasing voltage between the control gate CG and the drain. There are some proposals for the scheme for programming and erasing a plurality of nonvolatile memory cells by a single step.
Referring to FIG. 2, a first proposal of EEPROMs called FLOTOX (floating gate tunnel oxide) is such that a plurality of word lines WL and a corresponding number of source lines SL are provided in combination for respective rows of the memory cells, whereas a gate line GL and eight bit lines BL are provided in combination for each eight columns of memory cells, such as memory cells M40 to M47. For simplicity, only one byte of memory cells which have a similar configuration are shown in the drawing.
The EEPROM has a byte selection transistor Tr14 for each byte, or memory cells M40 to M47, and each memory cell has therein a cell selection transistor Tr13 and a cell transistor Tr15 having a FLOTOX structure for storage of data. Each of transistors Tr13, Tr14 and Tr15 is implemented by an n-channel transistor.
The cell selection transistor Tr13 of each memory cell has a gate connected to a word line WL, and a source-drain path connected between the bit line BL and the drain of the cell transistor Tr15. The byte selection transistor Tr14 has a gate connected to the word line WL, and a source-drain path connected between the gate line GL and the control gate of the cell transistor Tr15. The cell transistor Tr15 has a source connected to the common source line SL disposed for each byte of the cell transistors M40 to M47. The cell transistor Tr15 has a thin gate oxide film disposed between the floating gate FG and the semiconductor substrate for enabling programming and erasing by a tunnel effect of electrons from/into the floating gate.
FIGS. 3 to 5 show three different modes of eight memory cells M40 to M47 of the EEPROM shown in FIG. 2, including a programming mode, a flash erasing mode and a read mode. FIG. 6 shows applied voltages in each mode of FIGS. 3 to 5, which is effected in an ordinary manner in the EEPROM, i.e., a byte by byte manner.
In the programming mode, as shown in FIGS. 3 and 6, specified bit lines, among bit lines BL1 to BL8, corresponding to selected memory cells which are to be programmed (programmed with "0") are biased at Vpp (15 volts, for example), while the specified word line WL1 is biased at Vpp to turn on the selection transistors Tr13 and Tr14, the specified source line SL1 is open or floated, and the gate line GL is biased at zero volt. As a result, the electrons stored on the floating gates FG are withdrawn to thereby program the selected memory cells with "0". For memory cells to be erased (or programmed with "1") and memory cells not selected at this time, the corresponding bit lines among bit lines BL1 to BL8 are biased at zero volt, whereby these memory cells are erased or remains in the previous state. At this stage, word lines corresponding to the unselected memory cells are biased at zero volt.
In the flash erasing mode, as shown in FIGS. 4 and 6, the bit lines BL1 to BL8 are biased at 1 volt, while the specified word line WL1 is biased at Vpp to turn on the selection transistors Tr13 and Tr14, the source line SL 1 is floated, and the gate line are biased at Vpp. As a result, electrons are injected into the floating gates of selected memory cells for flash erasing. In this stage, the gate lines and word lines for unselected memory cell groups are biased at zero volt.
In the read mode, as shown in FIGS. 5 and 6, specified bit lines corresponding to the selected memory cells among bit lines BL1 to BL8 are biased at 1 volt, while the specified word line WL1 is biased at Vdd to turn on selection transistors Tr13 and Tr14, and specified source line SL1 and gate line GL are biased at zero volt. As a result, the electrons on the floating gates of selected memory cells can be detected through the bit lines BL1 to BL8 for judging a programmed state or an erased state for each of the selected memory cells. At this stage, bit lines corresponding to unselected memory cells are floated, whereas the gate lines corresponding to the unselected memory cells may be at zero volt or may be about 1 to 2 volts.
In the first proposal, there is a disturbance between the source and the floating gate because the source of the cell transistor Tr15 is directly connected to the common source line disposed for the memory cells M40 to M47. In the programming mode wherein electrons are withdrawn from the floating gate by applying a programming voltage to the drain of the cell transistor Tr15, the cell transistor Tr 15 assumes a depletion state wherein the threshold voltage of the cell transistor Tr15 is below zero volt. This causes a potential rise of the source of the cell transistor Tr15 up to .vertline.Vtm.vertline., which enters to the sources of other cell transistors of unselected memory cells via the source line SL. As a result, the disturbance is caused wherein the electrons stored in the floating gates FG of the other cell transistors are withdrawn by the positive voltage .vertline.vtm.vertline. of the sources to lose the stored data in the unselected memory cells.
A second proposal, which is described in Patent Publication JP-A-7-288291, is such that the memory cell has a single layer gate structure. The proposed EEPROM uses a Fowdler-Nordheim tunnel effect, similarly to the first proposal, for injecting/withdrawing electrons between the floating gate and the drain. Referring to FIG. 7, the proposed EEPROM has a plurality of word lines WL and a corresponding number of program lines PL disposed in combination for respective rows of memory cells, such as memory cells M30 to M37, and a selecting circuit for selecting memory cells specified by is address signals among the memory cells. Eight bit lines BL and a drain-gate line DGL, which functions as a common bit line for a byte of memory cells, are provided for each byte including eight memory cells M30 to M37.
Each of memory cells M30 to M37 has a selection transistor Tr11 and a cell transistor Tr12, both of which are n-channel MOSFETs.
The selection transistor Tr11 has a gate connected to a corresponding word line WL, and a source-drain path connected between a corresponding bit line BL and the source of the cell transistor Tr12. The cell transistor Tr12 has a drain and a control gate CG both connected to the drain-gate line 34. A part of the floating gate FG extending from the cell transistor tr12 forms a capacitive coupling between the same and a diffused region called a program area Pt.
FIG. 8 shows applied voltages in each mode of the EEPROM of FIG. 7, wherein programming, flash erasing and read modes are effected byte by byte. In the programming mode, the bit line BL for selected memory cells are floated, while the word line WL is biased at zero volt to turn off the selection transistor Tr11, the program line PL is biased at Vpp (15 volts, for example), and the drain-gate line DGL is biased at zero volt. As a result, stored charge is withdrawn from the program area Pt, whereby the selected memory cells are programmed. At this stage, unselected memory cells remains in the previous state by biasing the corresponding drain-gate line DGL at Vpp/2.
In the flash erasing mode, all the bit lines BL are floated while the specified word line WL is biased at zero volt to turn off the selection transistor Tr11, the program line PL is biased at zero volt, and the drain-gate line DGL is biased at Vpp. As a result, electrons are injected into each program area Pt for flash erasing.
In the read mode, the specified bit lines BL corresponding to the selected memory cells are biased at 1 volt, while the specified word line WL is biased at Vdd (5 volts, for example) to turn on the selection transistor Tr1, and the program line PL and the drain-gate line DGL are biased at zero volt. As a result, the electrons stored in the program area Pt are detected through the bit lines BL for judging the cell data.
In the second proposal, the drain of the cell transistor Tr12 and the program area Pt are driven by the drain-gate line DGL and the program line PL, which function as common bit lines. Thus, in the programming/erasing of selected cell transistors Tr12, there is a possibility that the drains and the program areas Pt of cell transistors of unselected memory cells may be also driven by the common bit lines to cause a disturbance similarly to the first proposal.